Karthik Kalia ¹, Md. Atiqur Rahman ¹, Dil M. Akbar Hussain ², Abhay Saxena ³, Mandeep Singh Walia ⁴

Affiliations
1 Gyancity Research Lab, Trikuta Nagar, Jammu - 180012, Jammu and Kashmir, IN
2 Aalborg University, DK
3 Dev Sanskriti Vishwavidyalaya, Haridwar - 249411, Uttarakhand, IN
4 Mahant Bachittar Singh College of Engineering and Technology, Jammu - 181101, Jammu and Kashmir, IN

Abstract

Background/Objectives: In this paper we will be discussing about the impact of technology on our daily lives. How everybody is dependent upon technology in one or other way. Methods/Statistical Analysis: Technology has played a significant role in the evolution of the society. Science has produced many new ideas but to harvest those ideas, technology is a must. With the huge requirement of engineering equipment's, the industry needs specialists who can manage and operate these technologies. Detailed information about the merits and demerits of technology is also mentioned in this paper. Findings: Technology has affected the environment on a great scale; in some cases, technology is even replacing human being or use of manpower. So proper counter measures have been mentioned, which can be used to control and limit harmful effect.

Keywords

3 R’s, Advanced Technology, Computation, E-waste, Engineering.

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Bishwajeet Pandey ¹, Md. Atiqur Rahman ¹, Dil M. Akbar Hussain ², Abhay Saxena ³, Bhagwan Das ⁴

Affiliations
1 Gyancity Research Lab, IN
2 Aalborg University, DK
3 Dev Sanskriti Vishwavidyalaya, Haridwar, IN
4 UTHM, MY

Abstract

The 8-bit design is able to process 256 times input combination in compare to 4-bit vedic multiplier, using approximates 6 times basic elements, 2 times IO buffers, approximate 1.5 times total power dissipation. HSTL_I_12, SSTL18_I and LVCMOS12 are the most energy efficient IO standards in HSTL, SSTL and LVCMOS family respectively. Device static power and design static power are two types of static power dissipation. Device static power is also known as Leakage power when the device is on but not configured. Design static power is power dissipation when bit file of design is downloaded on FPGA but there is no switching activity. Design static power dissipation of 8-bit Vedic multiplier is almost double of design static power dissipation of 4-bit Vedic multiplier. Device static (leakage) power dissipation of 8-bit Vedic multiplier is almost equal to device static power dissipation of 4-bit Vedic multiplier on 40nm FPGA.

Keywords

HSTL, IO Standards, LVCMOS, SSTL, Static Power Reduction, Vedic Multiplier, Voltage Scaling.

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